Low Power Design Techniques for today’s VLSI/ULSI chips

Low Power Design Techniques (from Sorin Dobre UCSD lecture)

User experience perspective

– Active Usage Time is the time interval to perform various tasks (audio play, voice calls, web browsing, video playback and game play) between two full battery charges

– Standby Time is the time interval ready to be activated.  Normally, this means only the radio is still occasionally running with the local cell towers to maintain time synchronization.  Other  functional tasks are not running. Minimize the leakage power will maximize the standby time.

Electrical Power Efficiency

– Power consumption to perform a set of tasks relative to performance targets,

– measured in (mW / MHz or mW / Perf target like mW / MIPS ) (MIPS = millions of instructions per second)

– Average power consumption

– Peak power consumption

Power consumption in digital systems

– Ptotal = Pactive + Pleakage

– Pactive = Pinternal + Pswitching

– Pswitching = aCV**2f (a = activity factor, C = capacitive load, V = voltage, f = frequency)

– Pinternal =  power consumed when input to CMOS gate changes but output does not change

Methods to reduce dynamic power (Pswitching)

– Reduce power supply voltage ( V )

– Reduce voltage swing in all nodes

– Reduce the switching probability (transition factor)

– Reduce load capacitance

 

Low power implementation in today’s VLSI/ULSI chips require a holistic and concurrent approach
that includes collaboration and methodology between:
System level design
Architectural design
Software Hardware co-design
IP design:
–  Circuit design
–  Physical implementation of the IP
Physical design (chip/block level)
– Power verification and modeling
– Silicon correlation and validation

System Optimization

Power delivery network optimization:
– On die vs on board (PCB) voltage regulators
– Voltage regulators efficiency
– Voltage rails definition
– System level power management:
– Adaptive voltage scaling (AVS)
– Dynamic clock frequency and voltage scaling (DCVS)
– Static voltage scaling (SVS)
Analog vs digital processing system level optimization
Optimization at the system with the goal of moving most of the signal processing
(data transformation) in the digital domain. The power consumption in the digital
domain is scalable with the process technology scaling and with the system use
mode requirements.
Digitally assisted analog processing

Architectural Optimization

Memory hierarchy
On die vs. off die memory
Cache size (miss penalty)
Cache hierarchy (architecture)
Address space definition

Processor architecture
Von Neumann , Harvard
VLIW (high IPC)
16bit, 32bit, 64 bit instruction architecture (IA) (Code compression)
In order vs out of order execution
Superscalar implementation
Multi thread implementation
Scalability : Single core vs. Multi core
Application specific IA optimization
– FFT cores
– Multipliers, adders ,shifters

Hardware accelerators:
Graphic 2D, 3D
Video encoder/decoder (720p, 1080p, 2160p)
Multimedia display
Audio + DSP (digital signal processing unit)
Modem baseband

Bus architecture
AHB implementation (Advanced high performance bus)
AXI
Fabric (high speed, high bandwidth interconnect):
– Bandwidth
– Latency
– Power

Clocking architecture:
PLL’s
Frequency planning
Clock architecture
Synchronous vs asynchronous clocks

IO interfaces
DDR3 (LPDDR3), SDIO
PCIE, USB, MIPI, HDMI, DISPLAYPORT, GPIO, RGMIII
Engineering system level design and optimization (ESL):
Algorithmic driven hardware implementation and optimization
System level power modeling
Hardware software co-design and optimization

 

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