Synchronizers for Asynchronous Signals

Asynchronous signals causes the big issue with clock domains, namely metastability.  This is a situation where the clock domain trying to capture the asynchronous event goes into a metastable state.  Is the asychronous signal a logic “1” or a logic “0” state?  For now we ignore the voltage value because metastability is independent of voltage.

Metastability cannot be prevented but it can be reduce.  High-speed digital circuits rely on synchronizers to create a time buffer for recovering from a metastable event, thereby reducing the possibility that metastability will cause a circuit to malfunction.

EDA companies such as Synopsys,Cadence and Mentor Graphics, create software to automatically read verilog code and detect synchronization problems.  The number one rule is to NOT synchronize inputs by more than one synchronizer.   The outputs of multiple synchronizers can produce different synchronized signals.

There are two basic types of synchronizers: 1) Asynchronous signal wider than the clock period of the synchronizer clock domain and 2) Asynchronous signal smaller than the clock period of the synchronizer clock domain.

Asynchronous signal > Synchronizer clock period

SYNC_SS

If designed into an ASIC (Application Specific Integrated Circuit), this synchronizer is typically put into a special library cell to keep the two back to back D flip-flop close to each other functionally and to minimize any clock skew in the ASIC.  In addition, as a rule of thumb, this synchronizer usually has a special cell name like “sync_ss”, meaning synchronize slow input signal.

Verilog code for above synchronizer

module sync_ss (clk, async_in, reset);

input clk, async_in, reset;

output synch_out;

always @(posedge clk)

if (reset)

meta <= 1’b0;

sync_out <= 1’b0;

else

meta <= async_in;

sync_out <= meta;

endmodule

 

Asynchronous signal < Synchronizer clock period

SYNC_HS

Similar to the circuit above, this synchronizer is typically put into a special library cell to keep the D flip-flops and special logic close to each other for functionality purposes and to minimize any clock skew in the ASIC.  In addition, as a rule of thumb, this synchronizer usually has a special cell name like “sync_fs”, meaning synchronize fast input signal.

 

 

 

 

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