Archive for January, 2011

Tips for Area Reduction using Synopsys DC and Cadence RTL Compiler Tools

January 11, 2011

Area = Cost = Pricing $$

So the smaller one can make a die with minimal defects, the less expensive one can sell to consumers.

The following are tips for minimizing area when using the two most popular hardware logic synthesis tools :  Synopsys DC / DC Ultra and Cadence RTL Compiler

Synopsys DC

set_max_area  -ignore_tns (ignore total negative slack and optimize for area)

report resources (reports arithmetic elements used for synthesis to allow one to target specific files with many arithmetic elements)

set compile_enhanced_resource_sharing true (share common arithmetic operators)

compile –area_effort high –auto_ungroup area

Synopsys DC Ultra

compile_ultra –area_effort_high_script  (between 8% to 33% area savings)


Synopsys DC Optimization Reference Manual (Page 52/233)

Optimizing for Area

The area optimization process minimizes the area your design uses.

The process tries to improve area, if that can be done without degrading delay cost.

Area optimization requires that you set an area constraint, using the set_max_area command.

By default, area optimization does not create a new timing violation or worsen an existing timing violation to gain an improvement in area.

If Design Compiler can identify a change to a path with a timing violation,

it makes the change only if it can improve area without worsening the timing violation.

Achieving the smallest design can require changes in optimization strategy or rewriting the HDL code.

Some strategies that can help achieve small designs are: • Ungroup all or part of the hierarchy.

Take care not to ungroup regular structures such as adders.

In particular, ungroup smaller blocks to allow shared optimization across boundaries.

See “Removing Hierarchy” on page 3-16.

• Automatically ungroup small hierarchies by using the compile_ultra command

or the -auto_ungroup area option of the compile command.

See Chapter 4, “Automatic Ungrouping.”

• Optimize across hierarchical boundaries.

See “Optimizing Across Hierarchical Boundaries” on page 3-8.

• Disable total negative slack optimization by using the -ignore_tns option of the set_max_area command.

See “Disabling Total Negative Slack Optimization” on page 3-8.

• Use the -area_effort high option or map_effort high option of the compile command.

• Use the -area_effort_high_script option of the compile_ultra command.

What flow and commands are recommended for area optimization in RC?


What is the optimal flow/commands recommended for Area Optimization in RC?


The main focus of RC is to optimize on timing.  There is no concrete flow or command to tell the tool just optimize based on area.

To achieve better area, look for the following:

1. Remove any repetitive hierarchy and preserves (don’t modify or don’t touch) if they are not needed.

2. Ungroup smaller blocks using small_ungroup command.

3. Check if proper complex library cells are selected when needed.

4. Check if there any datapath elements in the critical path with preserve attributes.

5. Avoid using the segmented wire-load mode if necessary.

Another technique involves the following:

1. make all the clocks two times slower (if You have a 5ns clock, make it 10ns).

For datapath RTL code,

set_attr dp_area_mode true /

2. set incremental_opto 0

3. synth -to_map  -effort high

4. put the initial constraints

5. synth -to_map -incr -effort high

You can also try, ‘set global_area 9’ and ‘synth -to_gen -eff medium’ instead of high.

What is “set global_area” attribute and how does it affect the area?

Why does setting “synth –to_gen –eff medium” affect the area?

That’s an internal command and does not always give a better area.

What it does is increasing to iteration steps in optimizing for area, you can try to see if it gives better area.

The ‘syn –to_gen’ effort controls the optimization of datapath.

In high effort, it will use more aggressive CSA algorithm for faster speed, and might result in larger area.