The purpose of the Synopsys Primetime tool is to analyze timing delays due to the inherent physical delay of the CMOS gate and due to the timing delays that interconnect the CMOS gates together.
Additionally, Primetime is used to analyze “derating” factors which can affect the localized area of the semiconductor chip due to number of gate delays and wiring. Traditionally, the old method was to “derate” the entire cell set which means all the cell delays would be delayed by say a factor of 0.9. This was overly pessimistic and did not accurately reflect the true delays. Over design will result in longer design cycles by trying to overcome an obstacle which cannot be overcome.
Instead, the current methodology is to use “context-specific” derating values which result in more accurate timing and shorter design cycle.
This applies only to 90nm and 65nm. It does not substitute for statistical static timing analysis.
See table below:
The methodology to apply for OCV is to perform graph-based OCV and then collect violating paths to perform path-based OCV.
See table comparing graph-based OCV to path-based OCV: